Block and unblock statement
Fpga Engineer Interview Questions
542 fpga engineer interview questions shared by candidates
Clock domain crossing, timing closure techniques, and hardware debug/test setups
Where do you see yourself in the future? (technical, leading, or managing)
Timing related questions, RTL design
Write the verilog code for a divide-3 counter with 50% duty cycle.
Mostly asked basic digital design questions. Draw a sequential circuit, what is the makeup of an FPGA (LE, Registers etc), Draw a mod 10 counter, draw the schematic for a half adder. Once i drew the schematic for it i was then ask to draw it as if i had only NAND gates.
About what I did in different jobs that I had
Technical questions: - Asked to code live in VHDL (screen-sharing). - General or semi in-depth discussion about DSP knowledge or how I would implement some DSP algorithms in VHDL.
what are the stages in fpga verification
1) Code an accelerator block in HLS according to a given specification, complete with Linux drivers and a user space programming interface. Discuss design choices, approach and tradeoffs. 2) Write RTL for a module counting the drift of a fast clock signal in relation to a high precision 1PPS-signal.
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