Quelle est la logique interne a une clock gating cell ?
Digitales Design Interview Questions
823 digitales design interview questions shared by candidates
Inverter VTC,STA pipelining and cache
Q: Tell me about a time when you didn't agree with someone else
Explain pipelining, how did I implement it in my RISC microprocessor project
Based on the project, how did you write the coverage in your system Verilog?
What's the 2 principle of Cache.
1. Tell me something about yourself. 2. Design a gate level circuit for given specification- To find even and odd no from 0 to 8 decimal no.(without using Kmap). 3. Rate yourself in Verilog. Write Verilog code for 2:1 mux then asked the difference between assign and always. 4. Explain the project of asic design of up counter(steps of rtl coding,floorplan,PnR,CTS,STA). 5. From project of D flip flop layout they asked me about DRC rule. 6. Asked me to draw structure of FinFet and then explain it. 7. Asked me to draw nmos and pmos and explain the difference. 8. What is the difference between short channel and long channel mosfet. 9. What is Floorplan and explain any algorithm. 10. Explain the setup and hold time in latch.
given a arbiter, a FIFO, 4 inputs, One flop how will you design a 4 stage pipeline structure.
design cycle and verification plan, polymorphism, inheritance, diff between python and perl, which to use when, blocking vs non blocking assignment, X vs Z in verilog, UVM phases, scoreboard vs monitor, etc
tell me about your previous experience
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