design a trafffic light controller
Digital Design Engineer Interview Questions
553 digital design engineer interview questions shared by candidates
Digital electronics questions, C programming questions, Combinational and sequential logic.
Design basic logic gates (AND, XOR) using a 2to1 mux. Write a module which will take clk as an input and output a clk divided by 3. Important to note that generated clock needs to be an output of the Flop.
RTL coding related questions such as writing a simple FSM.
How can I estimate a new IP complexity and area without having any specific details yet?
basic mosfet circuitry questions, got to know
Intro and things worked on. Then he asked me deep about the project I was working on. Synchronous FIFO question. Wrote for 50 continuous cycle s in any 100 cycles but reading every alternate cycles. Depth reqd? How to design synch fifo ? How async fifo ? Is it possible to write and read from sync FIFO built using single port sram in same clock cycle ? Setup time and why we need it ? How will multiply by 63 ? Optimize way of finding the square of a number ? 1, 4, 9, 16, 25,
How would you design and on odd counter and sequencer using dflip flops and gates.
Building a 3-input nand with 2-input nand, and some verilog questions, SV questions quesitons
hold setup time, metastabilità - clock divider - filtro fir - floating point
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