Most Qs is very basic calculation and concept
Design Verification Interview Questions
1,114 design verification interview questions shared by candidates
Current project architecture and role. SV and UVM related. SV constraint, coverage, assertions. UVM architecture and flow. Verification strategy related.
Questions were like: 1. Make 4:1 mux using 2:1 mux 2. Make and gate using 2:1 mux 3. Difference between asynchronous and synchronous reset. All the questions were like this only.
Introduce myself and previous experience
What is the difference between Mealy and Moore machines?
What will you do if you made a big mistake?
TECH: 1. write a code that generates a random phone number 2. You have 4 processes: A, B, C, D. If any of them finishes kill B. When all of them are finished print Done. (use fork join) 3. inheritance, asks you when a child had the same function as a parent what will it print when it is called. what is different when the function is virtual. can a child object be assignment to a parent and vice versa? after the assignment you call the function and they ask you what will be printed 4. make a sequence for burst write and read, for a 32 bit (I cant remember but there was a number here also?) K memory. (you need to write an item first and then show how it is used in the sequence)
write code which returns error if we got 10 packets within 10 seconds
Uvm phasing process, different phases in uvm
Print the relevant parts of this data file out in X,X,X format from a given list that has extra/missing bits of information.
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