I was asked to write system verilog constraints for a variety of random stimulus needs.
Design Verification Interview Questions
1,116 design verification interview questions shared by candidates
Questions on C++, Perl, System Verilog.
Register renaming
Difference between Verilog and SV. Difference between blocking and non-blocking. Inheritance and virtual functions. Many C codes such as reverse an array, reverse bits of a number, get all even bits of a number, Fibonacci series, generate a random floating point number between a and b, Find a number in an array for which sum of all elements to its left= sum of all elements to its right. Few questions on digital logic such as finding minimum gates required for a given truth table, sequence detector, generate AND gate from 2 input mux etc.
What is your experience with random constrained stimulus?
When in your previous work did you wish you behaved differently?
If you have a DC power supply in series with a 1k resistor and a 6k resistor, give the equation that described the voltage across the 6k resistor. Switch the 6k resistor for an inductor, what is the voltage across the inductor? Switch the inductor for a capacitor, what is the voltage across the 1k resistor? Change de the 1k resistor for a cap identical to the other one, what is the voltage drop across each cap? Change one of the caps to make it double the capacity of the other one, what is the voltage drop across each cap?
What did you do in your last job?
Write verilog code for any flipflop. variations were also asked.
crazy nonsense questions. How do you measure voltage of the wave from modelsim in gtkwave.? each question on each word in resume.
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