Explain the difference beteween Blocking vs Non-Blocking Assignments.
Design Verification Interview Questions
1,116 design verification interview questions shared by candidates
Typical Scoreboard Structure. What is an Analysis Port?
How to implement stimulus plan. Computer architecture concepts.
Some standard programming questions, hardware and power specific design questions, as well as test philosophy.
Given a 32 bit signal, create a SystemVerilog constraint that ensures that only 2 bits are flipped in randomization.
Give a logic expression to describe the relationship C = A > B
Scripting and programming interview was about file parsing and automation (Analyse the code, find the error, correct it) General keep an eye on digital design concepts like FSMs, Clock and Timing, CDC, etc.
Explain the structure of uvm verification environment.
Started with self introduction What's your role in project What is constraints Clocking block Modport FIFO Polymorphism
1. Difference between inter assignment and intra assignment delay 2. Blocking and Non- blocking procedural block 3. How to design AND gate using MUX 4. Signals used in FIFO. 5. Do FIFO required address or not? 6. What do you understand by synchronous and asynchronous circuit. 7. How can we disable the randomisation ? 8. Why we use virtual interface in verification environment? 9. How to select and give in the particular testcase which were generated in generator block?
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