They asked About Projects initially and then core
Design Verification Engineer Interview Questions
951 design verification engineer interview questions shared by candidates
Verilog Design based questions like: Difference between Mealy and Moore FSMs?
Should be clear with basics in System Verilog and UVM to clear the technical rounds. Interviewer mainly focus on projects and ask to implement uvm testbench components and explain the process
Do we run a sweatshop or do we play
Explain past job positions, what tasks you had to fulfill and how you did it.
Tell me about yourself.
They are ask about Protocols
Regarding testbench in sv and uvm
diff between blocking and non blocking
Father's name,basic qns, digital ,verilog
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