Basics of computer architecture, verification, data structures, rtl logic Telephonic interview was basics of RTL design
Design Verification Engineer Interview Questions
951 design verification engineer interview questions shared by candidates
question on packet transfer inside of test bench from generator to driver... (system verilog concepts)
When in your previous work did you wish you behaved differently?
There were 4 rounds - 3 technical and 1 HR.
If you have a DC power supply in series with a 1k resistor and a 6k resistor, give the equation that described the voltage across the 6k resistor. Switch the 6k resistor for an inductor, what is the voltage across the inductor? Switch the inductor for a capacitor, what is the voltage across the 1k resistor? Change de the 1k resistor for a cap identical to the other one, what is the voltage drop across each cap? Change one of the caps to make it double the capacity of the other one, what is the voltage drop across each cap?
What did you do in your last job?
what is blocking and non blocking?
crazy nonsense questions. How do you measure voltage of the wave from modelsim in gtkwave.? each question on each word in resume.
On projects and sv uvm based Protocol knowledge on what we mentioned in resume
mostly in uvm and sv
Viewing 591 - 600 interview questions