Digital design basics, SV, UVM, SVA
Design Verification Engineer Interview Questions
951 design verification engineer interview questions shared by candidates
Generate clock using always and forever in verilog
Describe how CAM (content addressable memory) works.
Write a function in C that receives a string with brackets i.e: "({})[]" and returns true if the brackets are in correct form (like the example above) or false if the brackets aren't well placed like for example : "((]["
Tell me about yourself and then questions on verilog
write constraint for memory system
Resume - past experiences and projects
He asked me about Data hazards, Instruction sets , Examples of branch prediction , 32 bit adder design. WAR and RAW Instruction examples. Basic Computer architecture questions.
All the questions were pretty basic and were related to fundamentals of logic design and verification.
Know everything in c++. Virtual functions/class. Polymorphism. Be ready to write code on the spot
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