That's all i can share . Practice your basics. All the best !
Design Verification Engineer Interview Questions
951 design verification engineer interview questions shared by candidates
Questions mostly about the project. Basics of Pcie protocol
Question about digital design and system verilog and uvm related questions
Computer Architecture, Logic design, validation, software, behavioral.
They asked about mu uvm design verification project
functional coverage, types of bins, types of array, constraint examples, virtual class,threads
Digital Logic, Computer Architecture, SystemVerilog, UVM, basic PERl
mux tree, FSM, Regions, NBA, DDR, Swapping of variables, crystal oscillator, full adder using 2x1 mux
Questions about debug of failure
power integrity understanding: including impedance threshold define and theory.
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