Most of the things were on ARM architecture, AMBA protocols, SV and UVM, Design concepts and Analytical skills
Design Verification Engineer Interview Questions
951 design verification engineer interview questions shared by candidates
Questions related to what you have mentioned on your resume. Digital concepts, FSM related questions, basic Setup and Hold time questions. I was asked a lot of general coding questions, SystemVerilog questions.
how would you code an adder in verilog
Tell me about your CV. Why do you want to work for us? Why do you want an internship and not a job?
1. Describe your current project, contribution and team structure? 2. Write Read and write transactions timing diagram of APB bus. With and without wait states? 3. Find the second largest in the integer array with single iteration. 4. Given a character array of 1000 elements, how do you find, how many times each of the character is repeated? 5. If there is any digital wave coming with random 0s and 1s, how do you find the time difference between 2 successive 1s? 6. Write full & empty conditions for FIFO. What are the verification scenarios of Asynchronous FIFO. 7. Behavioral questions related to personality and team.
SV and UVM related questions and ur understanding
what value the interviewee could supply to the company?
Q: SystemVerilog syntax questions Q: Design a clock in verilog without any existing clock signals Q: Some flip-flop/latch design questions at clock-domain crossing.
what did u understand about this Role?
Code C++ - to print Fibonacci series using C++
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