Given variable vector should be randomised as unique values but without using a system verilog keyword which is generally used
Design Verification Engineer Interview Questions
951 design verification engineer interview questions shared by candidates
digital electronics and verilog
How would you debug a failing simulation where coverage is not met?
Basic question in SV, UVM, Verilog, Linux
Why did you not raise alarm on a certain issue? (I didn't think it was that important, but the interviewer thinks it is very important - again a smile that hints that my team is not doing the right thing, according to him).
Compare Superscalar and VLIW processors.
1. Write a constraint to generate 4 variables which are unique
they focused a lot on OOP, which is unexpected given the title that I applied.
Do you know anything about RISC Architecture?
How would you write a test with randomized input (with bounds)?
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