To draw the schematic of several basic gates using pmos and most transistors
Design Digitale Interview Questions
823 design digitale interview questions shared by candidates
What is setup and hold time for a clock.
Digital Design frequently asked questions
Why did you choose to apply to Vodafone?
Design sequence detector with logic circuit diagram
They asked me questions related to Static Timing Analysis. For example, things like calculating setup time and hold time slack for a path in a digital circuit.
they asked me about basic STA, Verilog code to the circuit, and edge triggering-based questions also had some questions on the number system.
Basic Verilog code questions, such as latch inferences, correct assignations (not mixing blocking/non blocking), FSM, etc
CDC and related concepts. Clock main issues, metastability, glitching, etc, and the possible solutions
How to implement accumulators, multipliers in digital domain?
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