Intro and things worked on. Then he asked me deep about the project I was working on. Synchronous FIFO question. Wrote for 50 continuous cycle s in any 100 cycles but reading every alternate cycles. Depth reqd? How to design synch fifo ? How async fifo ? Is it possible to write and read from sync FIFO built using single port sram in same clock cycle ? Setup time and why we need it ? How will multiply by 63 ? Optimize way of finding the square of a number ? 1, 4, 9, 16, 25,
The interviewer was unprepared and was the person to interview me originally.
I was asked about one of my project that was on LMS adaptive filter (relevant to Digital Signal processing) and the hiring manager went deeper into the concepts of filter.
For the interview, it is very useful to know logic operations and how logic gates' I/O can be represented by logic operations. It is also very useful to know how certain expressions in verilog are translated into digital circuitry.
Current work-related and based on my Resume
Walk us through a project in your portfolio. How did you make this design decision? What tools did you use to make this?
How well do I know the tools mentioned in my resume?
It was digital design role. They asked cascode mosfets and questions on that.
FIFO problems.
I got lot of questions on async designs. Was surprised since was a new grad when I interviewed at Qualcomm, however were not that diffcult to answer. Was surprised there was very little focus on Architecture related questions as compared to other semiconductor companies I have interviewed in the past.
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