How to synchronize a data bus, which has no control. Interviewer was basically trying to poke at the approach to solve that problem. Write clock domain has a burst rate of 80 writes per 100 clocks. Read clock domain reads at a rate of 8 data words in 10 clocks. Data Buffer sizing to not cause overflow Asked to design a 2 request arbiter.
resume questions. coding questions(share screen)
Resume review questions were asked
Most important question was about Fifo depth
Example of previous project and designs
What was your past digital design experience? What qualified you for this role? What interested you in the company?
What are you looking for in your next role?
Why do you want to join TSMC?
1. Digital Design Questions. 2. Computer Architecture Basics
What type of simulator that I've used for the Verilog project
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