functional, code coverage ,priority encoder explanation, SV
Asic Verification Engineer Interview Questions
229 asic verification engineer interview questions shared by candidates
Calculate bandwidth for 16 bit data bus, data rate: 50 MHz and only 25% of time.
1. Some simple random stimulus with specified constraints
I had a phone screen - basic SV and UVM multiple choice questions. Second round - OOPs concepts, some verification concepts (types of coverage, stimulus).
System verilog, UVM scoreboard/monitor coding
Draw a FSM sequence detector
Basic electronics question - 2:1 Mux, truthtable, DFF, FPGA design flow
Read after write sequence implementation
Black box CRC circuit checking...
virtual memory standard libraries in C how to build a cache how will you move data in cache what is recursion linked lists, binary tree, flat architecture, how a CPU would work
Viewing 211 - 220 interview questions
See Interview Questions for Similar Jobs
Vlsi Design EngineerFpga Design EngineerAsic Design Verification EngineerHardware Asic Design EngineerVerification EngineerRtl Design EngineerSenior Vlsi Design EngineerFpga Verification EngineerSenior Asic Verification EngineerFpga EngineerFpga DeveloperVlsi EngineerLogic Design EngineerCharacterization EngineerPhysical Design EngineerFpga Development EngineerVerificatie Design EngineerDigital Asic Design Engineer