They asked me 1)about the various concepts of verifying a design and also provided me scenarios as to how we can verify them . 2)to explain my previous projects and my responsibilities for each of the projects . 3)Also, the software team asked me a programming example. There were various teams of people wanting me to explain my previous job profile and responsibilities and explaining me about their company culture. Overall, It was a very good experience for me since I was fascinated by the fact that my job profile and trading can coincide !! and how!
Asic Verification Engineer Interview Questions
229 asic verification engineer interview questions shared by candidates
Question regarding Logic design, Verilog ,State Machine- pattern detection, Comp Arch- Pipeline, hazards, cache, associativity, Basic Perl were asked.
Scripting questions on 2D hashes and asked for coding in perl/python. Basic questions on STA
My previous experience, as well as a few mock examples related to verification and what my process would be
I don't remember the question clearly but something that had to do with implementing some methods in a (UVM-like) Scoreboard class.
Node insertion in linked list. Fibonacci series function, hardware to generate Fibonacci series, prime number generation hardware , STA concepts, clock domain crossing, use of synchronizes, skew and setup hold time violation.
Explain past work experience and Project details.
I can't say exactly but one SystemVerilog question was to implement a finite state machine given a certain output. Review sequence detectors.
All questions were related to my previous experience, testing methodology, and problem solving skills. They also asked some basic oo concepts
what do u know about virtual pages
Viewing 171 - 180 interview questions