What are setup and hold time violations ? Showed me timing diagrams and asked me to explain the setup and hold times.
Asic Engineer Interview Questions
1,076 asic engineer interview questions shared by candidates
Why are you joining our company
setup/hold timing
They ask all basic questions about VLSI
They asked aptitude questions in the written test.
Tell me about your self
Verilog code for shift register.
How to determine if a taped out chip failed hold/setup timing
They asked me to complete a complex Verilog design, including testbench covering all conceivable corner cases, and a PowerPoint about it. It was obviously impossible to complete in the time allowed, so clearly part of the interview is to find out who submits to slave labor without complaint. Details of the design question are protected by NDA.
Why do you want to work for SpaceX?
Viewing 941 - 950 interview questions
See Interview Questions for Similar Jobs
Vlsi Design EngineerSenior Vlsi Design EngineerVlsi EngineerAsic Physical Design EngineerSenior Asic Design EngineerSoc Design EngineerRtl Design EngineerHardware Asic Design EngineerPhysical Design EngineerSenior Dft-ingenieurHardware Engineering ManagerHardware Asic Ontwerp IngenieurSenior Fpga Design EngineerFpga Design EngineerFpga Development EngineerSenior Hardware Design EngineerSenior Asic Fpga Design EngineerAsic Design Verification Engineer