- flip flop symbols - logic families
Asic Engineer Interview Questions
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4. How always @ (posedge reset or negedge clk) synthesized
2. CDC and Types of synchronizer
Focus mostly SystemVerilog, methodologies and server processor architecture.
Problem solving approach Core VLSI concepts
How can you reduce the delay of an inverter?
What is salicide layer? How is it related to self-aligned gates?
explain the project I did and DSP, FIR, FFT question
Setup and Hold time constraints
Counters, Flipflops, Latches, 32:8 Bit converter, State machine design, VHDL - Process statement, seuential logic, combo logic implementation, Functional coverage, code coverage - which coverage is crtitcal for verification sign-off and why ? , Different coding styles for FSMs, DV Environment diagram and explanation of last project in last company,.
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