No real difficul question. I assumed I d ok, though I ddn't te any feedback during te interview.
Asic Engineer Interview Questions
1,075 asic engineer interview questions shared by candidates
write a verilog code of moving average
Designing a master-slave circuit for a particular output waveform.
General questions about caches / memory systems.
They asked about click domain crossing what do I know?
Digital design basics, UVM structure, OOPs
How to implement accumulators, multipliers in digital domain?
A module has 3 input and 5 output ports. Had a discussion for rest of the interview on that design. Basically the interviewer was trying to understand what I need to come up with a design. Like, do you a clock, what are you control signals, what is the functionality etc
How to debug a timing violation in the lab?
They asked me questions related to Static Timing Analysis. For example, things like calculating setup time and hold time slack for a path in a digital circuit.
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