5/6 interviewers asked about past work experience, design problems, and analysis of circuits. One interviewer asked general get-to-know you questions.
Asic Design Engineer Interview Questions
709 asic design engineer interview questions shared by candidates
Fifo functionality and verilog code to write
What is the difference b/w create_clock and create_generated_clock?
never learned perl before so did not answer.
design a divide by 3 divider
About my understanding of layout tools, the environment and fluency on the design flow.
Tell me about yourself and work experience? Explain ASIC flow? What is Scan chain insertion? USe? What is scan chain reordering? Why macros are placed preferably at boundary and not at centre? What all physical only cells you cam across ? Explain? Checks before placement? How do you fix timing at Place? Difference between CCD and CTS? What is HFNS? Why it is not done at syn? Aim of CTS? What happens in route? What are NDR ? Explain side flows? Types of placement blockages? What is derate? what is LVS? what is FEV? Kind of buffers used for CTS? How do you select them?
Present the previous projects
Questions about clock domain crossing issues. How to avoid them.
How to verify a design? What do you know about your verification env? Do I know any AMBA protocol? Do I use shell script? or any other script language?
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