very detailed clock divided by three
Asic Design Engineer Interview Questions
710 asic design engineer interview questions shared by candidates
1st Round : Talked about RAW,WAW and WAR hazards and how is it solved/handled in both linear and OoO pipelines. Structural hazards caused and handled in OoO pipelines. 2nd Round: Was interviewed by 5 interviewers (45 minutes with each). Focussed entirely on my resume. Asked in depth questions on Tomasulo out of Order Implementation and Multi Clock Domain Fifo Design. Some of the questions were on Sequence Detectors, Simple Verilog design questions, Frequency Dividers and circuitry design. One of the interviewers gave a scenario and asked to wite a code to validate the integrity of the circuit (to test our VERIFICATION thinking ).
* A lot of computer architecture questions. * Some simple Verilog questions. * Few software related C/C++, compiler, perl scripting questions. * No behavioral/HR question at all.
mentioned above
what the keyword volatile means in C
they ask the inputs into the tools for different steps of physical design.
How do you access a private variable in a public class from another class in java.
Memory controller design
1. Circuit Design 2. Physical Design 3. Scripting
Know the details of your past work experience.
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