Projects discussion. Interview questions are based on STA, CMOS , Low power, Verilog coding Clock domain crossing, Clock Tree synthesis & Crosstalk
Asic Design Engineer Interview Questions
710 asic design engineer interview questions shared by candidates
Questions on constraints and assertions
Questions regarding library creating and area of the cells in the library
Designing multiple Gates or some basic logic using Multiplexers. Draw state Diagram & verilog code for 1010 sequence detector.
Antenna Effect, latch up
Question asked: SV -> function can take fork_join?y/n ->to find the bit to represent 4069 = 2^(x) or log 2 base (32) ->Malloc() ->write a integer queue : rand int q[$]; -> task and functions UVM: Sequencer- Driver connection phasing name 3 base class related question
Explain POCV coefficient based calculation for an actual timing report.
design uvm driver
Write an SV constraint to generate 4 non-overlapping memory regions of size 32,64,128,256 in 4k memory region.
1) What are slow and fast corners 2) Where we check Setup and Hold 3) FSM questions
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