We are hiring! Are you passionate about physical chip design and working through complex challenges? We need you! As a STA Engineer, you will create and verify block and top level timing constraints for multiple blocks and top level designs. Driving timing analysis and closure you will work with cutting-edge technology, collaborating closely with external IP providers, EDA vendors, and silicon/package vendors to deliver high-performance SoCs or SiPs for mass production.

What do we offer? Flexible work schedules, competitive pay, a highly collaborative learning environment, and opportunities for career growth. Come and join us in the beautiful city of Barcelona! Candies, coffee, and free Spanish lessons included! (Visa sponsorship available if required.).

Key Responsibilities

• Working in advanced technology nodes on block level and very large hierarchical designs.
• Working with design teams to develop block and top level constraints.
• Able to analyze constraint quality and constraint coverage for constraints provided by internal and third party vendors, variously at IP, block and top level.
• Ability to quickly and effectively analyze sta results, drive timing closure, generate timing ECO scripts for block and top level physical partitions.
• Work closely with block owners and CAD teams to push timing fixes to blocks.
• Provide expertise and knowledge to the wider design and implementation teams for STA and timing closure.
Responsibilities include working with
• engineers assisting them closing block level timing in physical design and STA..
• An ability to setup tool flows if required, including distributed processing task.

If you are ready to take on a role in one of the most exciting fields of chip design, apply now!

• Master’s or PhD degree in Computer Science, Microelectronics, or Physics.
• Proven experience with multiple tapeouts of high-performance SoCs or SiPs.
• Experienced in using revision control systems, preferably GIT.
• Extensive experience using Synopsys Primetime, including DMSA for analyzing multiple scenarios simultaneously.
• High level of TCL proficiency to analyze areas of interest in the timing domain
• Clear understanding and experience in dealing with very large hierarchical designs to include
  • Budgeting flows
  • Awareness of context in creating block constraints
  • Using Hyperscale or other techniques for handling huge designs
  • Knowledge of distributed processing / threading options in Primetime
• Experience with PrimeClosure would be an advantage