How to deal with clock domain crossing issues, timings in logic circuits etc
Verification Interview Questions
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Convert the RTL logic to a gatelvel netlist. Constraint question from system verilog.
Write a complex asserino
Describe loading speed
round robin algorithm, scheduling? state diagram?
if you have 2 masters and 4 slaves, what properties can you write to check the function?
advantages of mealy and moore
Black box CRC circuit checking...
What is your weakest quality?
virtual memory standard libraries in C how to build a cache how will you move data in cache what is recursion linked lists, binary tree, flat architecture, how a CPU would work
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