What is the angle between the minutes and hours hands at 3:15?
Digital Design Engineer Interview Questions
553 digital design engineer interview questions shared by candidates
Write VHDL for D Flip Flop Implement Cmos transistors to make an inverter
Difference between flip-flop and latch. What is jitter, clock skew? causes of jitter. What is metastability?
Would you do anything differently if you could start you thesis again?
Quelle est la logique interne a une clock gating cell ?
Explain pipelining, how did I implement it in my RISC microprocessor project
What's the 2 principle of Cache.
1. Tell me something about yourself. 2. Design a gate level circuit for given specification- To find even and odd no from 0 to 8 decimal no.(without using Kmap). 3. Rate yourself in Verilog. Write Verilog code for 2:1 mux then asked the difference between assign and always. 4. Explain the project of asic design of up counter(steps of rtl coding,floorplan,PnR,CTS,STA). 5. From project of D flip flop layout they asked me about DRC rule. 6. Asked me to draw structure of FinFet and then explain it. 7. Asked me to draw nmos and pmos and explain the difference. 8. What is the difference between short channel and long channel mosfet. 9. What is Floorplan and explain any algorithm. 10. Explain the setup and hold time in latch.
Was asked to describe Projects in Resume,FIR vs IIR, Sampling theorem
Questions related to Basic Digital Design, Clock Dividers, Clock Domain Crossing(Very imp!!), RTL coding, FSMs, Valid - Ready protocols, Synthesis, Static timing analysis, Physical Design Fundamentals, Little bit Architecture, very basic analog touch up (easy), very few DSP related questions(easy)
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