C++, SystemVerilog basics
Design Verification Engineer Interview Questions
951 design verification engineer interview questions shared by candidates
Confidential. But related to system verilog and uvm.
Describe your previous projects and describe your contribution in them
I don't remember the question clearly but something that had to do with implementing some methods in a (UVM-like) Scoreboard class.
Design verification lifecycle out of order scoreboard
Implement a state machine that detects modulo 5
design a vending machine from architecture to rtl..
1. Constraint random, assertions, UVM env 2. OOPS concept 3. Coverage, python scripting 4. Verilog and digital logic
Verilog code for the clock divider
about gates basic concepts of c and java
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