soc - c handshake mechanism/ how c testcase is getting completed
Design Verification Engineer Interview Questions
951 design verification engineer interview questions shared by candidates
Basics of Digital Electronics and Verilog
2 lists which are connected. find the joint element
2 rounds of Interview happened on the same day on call. Asked to code the monitor for a DUT. DUT was loaded with all the conditions with how it works which made it complex. SV constraint and some algorithm related questions were asked. All were of good quality.
static timing analysis
network theory
Define verilog ,systemverilog. Memory /cache
C++, SystemVerilog basics
if I talk to your previous boss, what he/she/they gonna say about you?
1. Constraint random, assertions, UVM env 2. OOPS concept 3. Coverage, python scripting 4. Verilog and digital logic
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