My previous experience, as well as a few mock examples related to verification and what my process would be
Asic Engineer Interview Questions
1,076 asic engineer interview questions shared by candidates
Mostly related to system verilog, verilog and in general Digital Logic.
They checked your resume and asked the questions related to your classes.
1st round: asked basic verilog questions like difference between wires & regs, difference between if-statements and case statements. Asked about projects on resume. Asked a small project and how I should approach it. 2nd round: gave a problem and had to create FSM and verilog.
Emerging technologies in the microchip industry
Current project architecture and role. SV and UVM related. SV constraint, coverage, assertions. UVM architecture and flow. Verification strategy related.
What is MOSFET, EDA etc.
ok. fifo..design n implementation.and other designing questions
What is a fpga and what is a lookup table?
What is your Ph.D. research?
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